01
Monocrystalline Epitaxial Structure
The epitaxial layer follows the substrate lattice orientation and maintains a continuous monocrystalline silicon structure.
SciMater™ Semiconductor Materials
SciMater™ Monocrystalline Silicon Epitaxial Wafers
A parameter-controlled monocrystalline silicon epitaxial layer is grown on a high-quality monocrystalline silicon substrate. Conductivity type, resistivity, dopant and thickness can be specified independently for the epitaxial layer and substrate, making the wafers suitable for power semiconductors, integrated circuits, discrete devices, optoelectronics, MEMS and microelectronics research.
4–8 in Common wafer sizes for research and device fabrication
6+ Key epitaxial-layer and substrate parameters can be specified separately
N / P Supports homo-type and hetero-type epitaxial combinations
Customizable Thickness, resistivity, orientation and surface requirements
Product Description
Product Description
Epitaxial Layer + Monocrystalline Silicon Substrate
A monocrystalline silicon epitaxial wafer is produced by growing a monocrystalline silicon layer on the surface of a monocrystalline silicon substrate through epitaxial processes such as chemical vapor deposition. The grown surface layer is the epitaxial layer, while the underlying wafer is the substrate.
Compared with standard polished silicon wafers, epitaxial wafers allow the conductivity type, resistivity, dopant concentration and thickness of the epitaxial layer and substrate to be controlled independently. Structures such as N⁻/N⁺, P⁻/P⁺, N/N, P/P, N/P and P/N can be produced to provide a controlled active layer, depletion region and low-resistance supporting substrate.
SciMater™ offers common 4-inch, 6-inch and 8-inch specifications. Epitaxial-layer thickness, resistivity, conductivity type, crystal orientation, substrate thickness, geometric parameters, surface defects and inspection documentation can also be evaluated according to project requirements.
Epitaxial wafers are specification-sensitive semiconductor materials. Final specifications should be verified against the order confirmation, product label, lot data sheet or inspection report. Wafer diameter alone should not be used to determine compatibility with a target device.
Core Features
Core Product Features
Clear, Specification-Based Design
02
Independently Controlled Parameters
Conductivity type, resistivity, dopant and thickness can be designed separately for the epitaxial layer and substrate.
03
Multiple Structures Available
Supports N/N, P/P, N/P and P/N structures, as well as lightly doped epitaxial layers on heavily doped substrates.
04
High-Quality Surface
The epitaxial surface is suitable for subsequent photolithography, etching, oxidation, implantation and metallization.
05
Selectable Thickness
Epitaxial thickness can be selected according to the device active region, depletion width and breakdown-voltage requirements.
06
Multiple Wafer Sizes
Common sizes include 4-inch, 6-inch and 8-inch wafers; other sizes can be evaluated.
07
Broad Process Compatibility
Compatible with subsequent diffusion, ion implantation, photolithography, etching, oxidation and thin-film deposition.
08
Lot Documentation Available
Epitaxial thickness, resistivity and substrate parameter documentation can be confirmed for the applicable product lot.
Product Comparison
Core Specifications of Available Products
Reference Prices Only
| Product Name | Size | Epitaxial Structure | Epitaxial Layer Type | Epitaxial Layer Orientation | Epitaxial Layer Dopant | Epitaxial Layer Resistivity | Epitaxial Layer Thickness | Substrate Type | Substrate Orientation | Substrate Dopant | Substrate Resistivity | Substrate Thickness | Source | Recommended Use | Price |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 4-Inch Epitaxial Wafer, Specification 2 | 4 in / Φ100 mm | Single-Layer Epitaxy | P-Type | 〈111〉 | Not Specified | 2–3Ω·cm | 12±0.05μm | N-Type | 〈111〉 | Sb | <0.02Ω·cm | 525±15μm | Standard Specification | P/N structures, diodes and device research | ¥200 |
| 4-Inch Epitaxial Wafer, Specification 3 | 4 in / Φ100 mm | Single-Layer Epitaxy | N-Type | 〈111〉 | Not Specified | 4–5Ω·cm | 10±0.05μm | P-Type | 〈111〉 | B | <0.02Ω·cm | 525±15μm | Standard Specification | N/P structures, optoelectronics and junction research | ¥200 |
| Imported 6-Inch Epitaxial Wafer | 6 in / Φ150 mm | Single-Layer Epitaxy | N-Type | 〈100〉 | P | 0.285–0.315Ω·cm | 6±0.3μm | N-Type | 〈100〉 | As | <0.003Ω·cm | 625±25μm | Imported | Low-resistance substrates, discrete devices and process development | ¥342 |
| 8-Inch Double-Layer Epitaxial Wafer | 8 in / Φ200 mm | Double-Layer N-Type Epitaxy | Double-Layer N-Type | 〈100〉 | P | Top Layer: 14.3 Ω·cm ±5%; Bottom Layer: 1.5 Ω·cm ±5% | Top Layer: 40 μm ±4%; Bottom Layer: 8 μm ±4% | N-Type | 〈100〉 | As | 0.003–0.005Ω·cm | 725±15μm | Double-Layer Structure | Power devices, high-voltage structures and vertical devices | ¥1700 |
Prices shown are references for currently available base specifications. Final pricing may vary with epitaxial thickness, resistivity, conductivity type, defect requirements, inspection items, import source and order quantity.
Wafer Structure
Monocrystalline Silicon Epitaxial Wafer Structure
Top to Bottom
Epitaxial Surface Surface for photolithography, etching, implantation and metallization
Monocrystalline Silicon Epitaxial Layer Primary Device Active Region
Transition Region Doping transition region between the epitaxial layer and substrate
Monocrystalline Silicon Substrate Mechanical support, current path and lattice foundation
| Structural Region | Primary Function | Key Parameters |
|---|---|---|
| Epitaxial Layer | Serves as the main device active region and controls carrier concentration, resistivity and breakdown-voltage performance | Conductivity type, resistivity, dopant, thickness and uniformity |
| Transition Region | Connects the epitaxial layer and substrate and is affected by epitaxial growth and subsequent thermal processing | Doping gradient, interface condition and diffusion depth |
| Monocrystalline Silicon Substrate | Provides mechanical support, a current path and the lattice foundation for epitaxial growth | Type, orientation, dopant, resistivity and thickness |
| Epitaxial Surface | Used for subsequent oxidation, photolithography, etching, implantation and metallization | Particles, haze, scratches, roughness and defects |
Technical Parameters
Main Technical Parameters
Confirmed by Order
| Parameter | Available Range and Description | Selection Considerations |
|---|---|---|
| Material | Monocrystalline silicon epitaxial layer + monocrystalline silicon substrate | Confirm that the epitaxial layer and substrate match the target structure |
| Common Sizes | 4 in, 6 in, 8 in and custom sizes | Match the equipment chuck, lithography system and wafer carrier |
| Epitaxy Configuration | Primarily single-side epitaxy; double-layer or special structures can be evaluated | Confirm single-layer, double-layer and interlayer parameters |
| Epitaxial Layer Type | N-Type, P-Type or customized for the device structure | Select according to the device active region and junction structure |
| Substrate Type | N-Type, P-Type, heavily doped or standard-resistivity substrate | Consider substrate conductivity and backside contact |
| Common Structures | N⁻/N⁺、P⁻/P⁺、N/N、P/P、N/P、P/N | The first designation refers to the epitaxial layer and the second to the substrate |
| Common Orientations | 〈100〉 and 〈111〉; consult us for other orientations | Match oxidation, etching and device processes |
| Epitaxial Layer Thickness | Thin, standard and thick epitaxial layers; exact ranges depend on process evaluation | Select according to breakdown voltage, junction depth and depletion width |
| Epitaxial Layer Resistivity | Low, standard, high or specified resistivity range | Balance breakdown voltage and on-state resistance |
| Substrate Thickness | Standard thickness or customized according to device, equipment and thinning requirements | Confirm mechanical strength and subsequent thinning process |
| Surface Condition | Finely polished epitaxial surface; backside condition confirmed by lot | Confirm front/back orientation, particle and defect requirements |
| Orientation Mark | Flat, notch or the applicable diameter standard | Match automated equipment and crystal-orientation recognition |
| Geometric Parameters | Thickness, TTV, bow and warp can be specified as required | Important for high-precision lithography and bonding |
| Packaging | Wafer carrier, clean bag, vacuum packaging or individual packaging | Select according to cleanliness and transportation requirements |
Structure Comparison
Comparison of Common Epitaxial Structures
Device Structure Reference
| Epitaxial Structure | Epitaxial Layer Characteristics | Substrate Characteristics | Common Applications |
|---|---|---|---|
| N⁻/N⁺ | Lightly doped N-type epitaxial layer | Heavily doped, low-resistance N-type substrate | Power diodes, power transistors and vertical devices |
| P⁻/P⁺ | Lightly doped P-type epitaxial layer | Heavily doped P-type substrate | Analog devices, discrete devices and specialized integrated structures |
| N/N | N-type epitaxial layer with independently specified resistivity | N-type substrate | Sensors, microelectronic devices and process research |
| P/P | P-type epitaxial layer with a controllable doping gradient | P-type substrate | CMOS, sensor and integrated-circuit research |
| N/P | N-type epitaxial layer | P-type substrate | Diodes, optoelectronic devices and P/N-junction research |
| P/N | P-type epitaxial layer | N-type substrate | Optoelectronics, sensing and specialized junction research |
Material Comparison
Epitaxial Wafers vs. Standard Polished Silicon Wafers
Quickly Determine Whether Epitaxy Is Required
| Comparison Item | Monocrystalline Silicon Epitaxial Wafer | Standard Polished Monocrystalline Silicon Wafer |
|---|---|---|
| Wafer Structure | Epitaxial Layer + Monocrystalline Silicon Substrate | Single monocrystalline silicon substrate |
| Parameter Control | Epitaxial-layer and substrate parameters can be designed separately | The entire wafer typically has one conductivity type and resistivity |
| Device Function | Can provide a doping gradient, device active layer and low-resistance supporting layer | Suitable for basic processing, film deposition and conventional devices |
| Manufacturing Process | Epitaxial growth is performed on a polished silicon substrate | Produced by slicing, grinding and polishing |
| Purchase Cost | Relatively higher and affected by epitaxial specifications and inspection requirements | Relatively lower |
| Common Applications | Power devices, integrated circuits, optoelectronics, sensors and demanding microelectronic devices | Photolithography, film deposition, MEMS, material characterization and teaching experiments |
| Selection Considerations | Epitaxial thickness, resistivity, conductivity structure, defects and substrate parameters | Crystal orientation, conductivity type, resistivity, thickness and polishing configuration |
Applications
Main Applications
Device and Research Applications
Power Semiconductors
Power diodes, MOSFETs, IGBTs and vertical power devices.
Discrete Devices
Diodes, transistors, rectifiers and switching devices.
Integrated Circuits
CMOS, bipolar integrated circuits, analog ICs and application-specific ICs.
Optoelectronic Devices
Photodetectors, photodiodes and photoelectric conversion devices.
MEMS & Sensors
Pressure, temperature, gas, biosensors and inertial sensors.
Micro- and Nanofabrication
Photolithography, etching, diffusion, ion implantation, oxidation and metallization.
Electrical Research
P/N junctions, carrier transport, breakdown and resistivity-gradient studies.
Academic Research
Research on semiconductor materials, device physics, microelectronics and epitaxial processes.
Selection Guide
How to Select a Monocrystalline Silicon Epitaxial Wafer
Match Specifications to the Application
| Application Requirement | Parameters to Confirm | Selection Guidance |
|---|---|---|
| Power Diode or Power Transistor | Epitaxial-layer type, thickness, resistivity and heavily doped substrate | Balance breakdown voltage and on-state resistance |
| P/N-Junction Device | Conductivity types, junction structure and doping of the epitaxial layer and substrate | Confirm the N/P or P/N combination and subsequent junction depth |
| CMOS or Integrated Circuit | Crystal orientation, epitaxial-layer resistivity, particles and defect level | Consider surface quality, uniformity and thermal budget |
| Photodetector | Epitaxial-layer thickness, resistivity, carrier lifetime and surface quality | Design according to absorption depth and response region |
| MEMS Sensor | Wafer thickness, epitaxial thickness, TTV, bow and warp | Match deep etching, membrane structures and bonding processes |
| Low-Leakage Device | Epitaxial purity, defects, resistivity and interface quality | Strictly control surface contamination and epitaxial defects |
| Vertical Conduction Device | Epitaxial-layer thickness, substrate resistivity and backside condition | Prefer a low-resistance, heavily doped substrate |
| General Research Testing | Size, epitaxial structure, thickness and resistivity | Selecting an available base specification can reduce purchase cost |
| Subsequent High-Temperature Processing | Dopant diffusion, epitaxial thickness, oxidation requirements and thermal budget | Prevent high temperatures from changing the target resistivity and junction structure |
Thickness Selection
How to Select Epitaxial-Layer Thickness
Thicker Is Not Always Better
| Epitaxial Layer Category | Main Characteristics | Common Applications |
|---|---|---|
| Thin Epitaxial Layer | A thin device active region suitable for shallow junctions and fine structures | Integrated circuits, sensors and small devices |
| Standard Epitaxial Layer | Balances electrical performance, thickness control and process stability | Diodes, transistors and conventional microelectronic devices |
| Thick Epitaxial Layer | Enables a wider depletion region and higher-voltage structure | Power devices, high-voltage devices and specialized sensor structures |
Epitaxial-layer thickness should be selected by considering breakdown voltage, on-state resistance, depletion width, carrier transport, junction depth and subsequent etch depth.
Usage Guide
Usage Guide
Clean Handling First
1
Incoming Inspection
Verify size, epitaxial structure, thickness, resistivity, substrate type, crystal orientation, quantity and packaging condition.
2
Identify the Epitaxial Surface
Use the label, wafer-carrier marking or lot instructions. Do not identify the epitaxial surface solely by brightness or color.
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Clean Handling
Wear powder-free gloves and handle the wafer from the edge with a vacuum wand or wafer tweezers. Avoid touching the central area.
4
Pre-Process Cleaning
Use clean containers and high-purity reagents appropriate for the downstream process to remove particles, organic residues and metallic contamination.
5
Photolithography & Etching
After dehydration and surface preparation, perform coating, exposure, development and etching. Avoid unintentionally etching through the epitaxial layer.
6
Oxidation & Implantation
Include thermal oxidation, diffusion and ion implantation in the process thermal budget to prevent shifts in doping distribution and resistivity.
7
Metallization
Select the metal system and annealing conditions according to conductivity type, contact structure and target contact resistance.
8
Dicing & Packaging
Protect the epitaxial surface before dicing, control particles, edge chipping and stress, and use clean individual packaging after dicing.
Precautions
Handling Precautions
Prevent Epitaxial-Surface Damage
| Precaution | Recommended Practice |
|---|---|
| Prevent Surface Scratches | Do not touch the central area with ordinary metal tweezers or place the epitaxial surface on a rough surface |
| Prevent Particle Contamination | Open, handle, clean and process the wafer in a clean environment whenever possible |
| Verify the Epitaxial Surface | Follow the package label and lot instructions to avoid using the wrong side |
| Control Process Depth | Set etching, grinding and thinning endpoints according to the epitaxial-layer thickness |
| Control the Thermal Budget | High-temperature oxidation, diffusion and annealing may change the doping profile and junction depth |
| Prevent Wafer Breakage | Avoid impact, bending, localized clamping and rapid temperature changes |
| ESD Protection | Apply electrostatic-discharge protection to processed devices and high-resistivity epitaxial wafers |
| Retain Lot Documentation | Record the lot number, epitaxial structure, thickness, resistivity and downstream process conditions |
Storage
Storage & Maintenance
Clean, Dry and Protected from Light
| Item | Storage Recommendation |
|---|---|
| Storage Environment | Store in a clean, dry and dark environment away from acid/alkali vapors and corrosive gases |
| Packaging | Keep unused wafers in the original wafer carrier, clean bag or vacuum packaging |
| After Opening | Use promptly after opening. Reseal remaining wafers and label them with the lot number and date |
| Surface Protection | Prevent direct rubbing between the epitaxial surface and paper, foam, ordinary plastic or other wafers |
| Long-Term Storage | Store in a clean dry cabinet and minimize repeated opening |
| Transportation and Handling | Use a wafer carrier or dedicated transport fixture; do not stack bare wafers for transport |
| Specification Management | Store the product together with its data sheet, lot label or inspection report |
Ordering Information
Recommended Information for Ordering
Reduce Repeated Specification Checks
Standard RFQ Format
Size + epitaxial-layer conductivity type + epitaxial-layer dopant + epitaxial-layer resistivity + epitaxial-layer thickness + substrate conductivity type + substrate dopant + substrate resistivity + crystal orientation + substrate thickness + quantity + inspection requirements
| Requirement Type | Information to Provide | Example |
|---|---|---|
| Standard Epitaxial Wafer | Size, epitaxial structure, thickness, resistivity, substrate parameters, orientation and quantity | 6 in + N-type epitaxial layer + 5–10 Ω·cm + 10 μm thick + N⁺ substrate + 〈100〉 + 10 wafers |
| Dicing Service | Target dimensions, quantity, dimensional tolerance, dicing method and packaging requirements | 10 × 10 mm + 60 pieces + laser dicing + clean individual packaging |
| Additional Processing | Oxide layer, metal film, backside thinning, drilling, patterning and inspection requirements | Front-side SiO₂, 300 nm + backside thinned to 400 μm + thickness report provided |
| High-Precision Devices | Particle, defect, TTV, bow, warp and epitaxial-uniformity requirements | TTV ≤ specified value + confirmed particle and epitaxial-defect grade |
FAQ
FAQ
Click to Expand
Q1: What is a monocrystalline silicon epitaxial wafer?
A monocrystalline silicon epitaxial wafer is made by growing an additional monocrystalline silicon layer on a monocrystalline silicon substrate. Conductivity type, resistivity, dopant and thickness can be designed separately for the epitaxial layer and substrate.
Q2: How is an epitaxial wafer different from a standard polished silicon wafer?
A standard polished silicon wafer normally consists of a single substrate. An epitaxial wafer has both an epitaxial layer and a substrate, allowing different resistivities, doping concentrations or conductivity types within one wafer.
Q3: What are the respective functions of the epitaxial layer and substrate?
The epitaxial layer usually serves as the main device active region, while the substrate provides mechanical support, a lattice foundation and a current path. Both should be designed together for the target device structure.
Q4: What do N⁻/N⁺ and P⁻/P⁺ mean?
The first designation normally refers to the epitaxial layer and the second to the substrate. “+” indicates a higher doping concentration, while “−” indicates a lower doping concentration.
Q5: How should epitaxial-layer thickness be selected?
Selection should consider breakdown voltage, depletion width, on-state resistance, target junction depth and subsequent etch depth. High-voltage devices generally require a relatively thick, lightly doped epitaxial layer.
Q6: Is higher epitaxial-layer resistivity always better?
No. Higher resistivity may improve the breakdown voltage of some devices, but it may also increase on-state resistance. The value should be balanced according to the device design.
Q7: Can epitaxial-layer thickness and resistivity be customized?
Customization can be evaluated according to wafer size, conductivity type, target thickness, resistivity, quantity and process feasibility.
Q8: Can N/P or P/N structures be customized?
Combinations of epitaxial layers and substrates with different conductivity types can be evaluated. Final feasibility depends on transition-region control, target specifications and device design.
Q9: Can the wafer be used directly for photolithography?
Epitaxial wafers are generally suitable for photolithography, but cleaning, dehydration and surface treatment are still recommended before high-precision processing according to the required cleanliness level.
Q10: Can epitaxial wafers undergo thermal oxidation?
Yes. Thermal oxidation consumes part of the surface silicon and may affect the doping profile, so temperature and time should be included in the device thermal budget.
Q11: Can epitaxial wafers undergo ion implantation?
Yes. Implantation energy, dose and annealing conditions should be designed according to epitaxial-layer thickness, resistivity and target junction depth.
Q12: Can metal be deposited on an epitaxial wafer?
Metals such as Au, Al, Ti, Pt and Ni can be deposited, but the metal system and annealing conditions should be selected according to material type, contact structure and target contact resistance.
Q13: How can the epitaxial surface be identified?
Use the product label, wafer-carrier marking, lot instructions or specification documents. Do not rely solely on color, brightness or visual inspection.
Q14: Can epitaxial wafers be diced into smaller pieces?
Yes. Mechanical scribing, DISCO dicing or laser dicing can produce square, rectangular or other dimensions. Protecting the epitaxial surface before dicing is recommended.
Q15: Does dicing affect the epitaxial layer?
Dicing can create edge chipping, particles, stress and localized defects near the cut edge, but it generally does not affect the usable region away from the edge.
Q16: Can an inspection report be provided?
Epitaxial-layer thickness, resistivity, conductivity type, substrate parameters and surface-quality documentation can be confirmed according to the product lot and order requirements.
Q17: Why can wafers of the same diameter have very different prices?
Price is also affected by epitaxial-layer thickness, resistivity, conductivity structure, substrate parameters, defect requirements, uniformity, import source, inspection items and order quantity.
Q18: Are epitaxial wafers suitable for power devices?
Yes. A lightly doped epitaxial layer combined with a heavily doped, low-resistance substrate is a common structure for many vertical power devices. Exact parameters should be designed according to breakdown-voltage and on-state-resistance requirements.
Summary
Product Summary
Base Selection on Lot Specifications
SciMater™ monocrystalline silicon epitaxial wafers use a parameter-controlled monocrystalline silicon layer grown on a monocrystalline silicon substrate, allowing the conductivity type, resistivity, doping concentration and thickness of the epitaxial layer and substrate to be designed separately. They are important base materials for research on power semiconductors, discrete devices, integrated circuits, optoelectronics, MEMS and sensors.
When ordering, confirm wafer size, epitaxial-layer conductivity type, epitaxial-layer thickness, resistivity, substrate type, crystal orientation, surface quality and downstream processing conditions. For power devices, focus on epitaxial-layer thickness, resistivity and substrate conductivity. Integrated-circuit and sensor applications should also consider particles, defects, TTV, bow and warp.
