High-purity, undoped monocrystalline silicon substrates with a low carrier background. Available as single-side polished, double-side polished, full wafers, ultra-thin wafers, diced pieces, and custom specifications for RF and microwave devices, terahertz research, infrared optics, MEMS, thin-film materials, and low-leakage device studies.
Intrinsic high-resistivity monocrystalline silicon wafers are manufactured from high-purity single-crystal silicon. By controlling impurities and intentional dopant concentrations during crystal growth, the wafers provide high resistivity, low free-carrier concentration, and a low electrical background. They are suitable for research and device fabrication where substrate leakage, parasitic coupling, free-carrier absorption, and conductive background interference must be minimized.
Reduces the influence of the silicon substrate on electrical measurements of films, electrodes, and devices.
Suitable for low-leakage, high-frequency, RF, microwave, and terahertz research.
SSP is suitable for conventional processing, while DSP supports transmission, bonding, and double-sided processes.
Available as full wafers, ultra-thin wafers, square pieces, round pieces, and other custom dimensions.
Full wafers, ultra-thin wafers, custom-parameter products, and diced pieces are shown in one table for quick comparison of dimensions, polishing, thickness, and price.
| Product Category | Specification | Polishing | Thickness | Description | Price (CNY) |
|---|---|---|---|---|---|
| Full Wafer | 1 Inch | Single-Side Polished | Standard Thickness | Intrinsic Undoped Monocrystalline Silicon Wafer | 100 |
| Full Wafer | 2 Inches | Single-Side Polished | Standard Thickness | Intrinsic Undoped Monocrystalline Silicon Wafer | 100 |
| Ultra-Thin Wafer | 2 Inches | Single-Side Polished | 100μm | Intrinsic Undoped Ultra-Thin Monocrystalline Silicon Wafer | 300 |
| Full Wafer | 2 Inches | Double-Side Polished | Standard Thickness | Intrinsic Undoped Double-Side Polished Monocrystalline Silicon Wafer | 110 |
| Custom Parameters | 2 Inches | Confirmed on Request | Customized on Request | Custom crystal orientation, resistivity, thickness, and related parameters | 100 |
| Full Wafer | 3 Inches | Single-Side Polished | Standard Thickness | Intrinsic Undoped Monocrystalline Silicon Wafer | 150 |
| Full Wafer | 3 Inches | Double-Side Polished | Standard Thickness | Intrinsic Undoped Double-Side Polished Monocrystalline Silicon Wafer | 160 |
| Custom Parameters | 3 Inches | Confirmed on Request | Customized on Request | Custom crystal orientation, resistivity, thickness, and related parameters | 150 |
| Full Wafer | 4 Inches | Single-Side Polished | Standard Thickness | Intrinsic Undoped Monocrystalline Silicon Wafer | 180 |
| Full Wafer | 4 Inches | Double-Side Polished | Standard Thickness | Intrinsic Undoped Double-Side Polished Monocrystalline Silicon Wafer | 190 |
| Custom Parameters | 4 Inches | Confirmed on Request | Customized on Request | Custom crystal orientation, resistivity, thickness, and related parameters | 180 |
| Full Wafer | 5 Inches | Single-Side Polished | Standard Thickness | Intrinsic Undoped Monocrystalline Silicon Wafer | 260 |
| Full Wafer | 6 Inches | Single-Side Polished | Standard Thickness | Intrinsic Undoped Monocrystalline Silicon Wafer | 280 |
| Full Wafer | 6 Inches | Double-Side Polished | Standard Thickness | Intrinsic Undoped Double-Side Polished Monocrystalline Silicon Wafer | 290 |
| Custom Parameters | 6 Inches | Confirmed on Request | Customized on Request | Custom crystal orientation, resistivity, thickness, and related parameters | 280 |
| Full Wafer | 8 Inches | Single-Side Polished | Standard Thickness | Intrinsic Monocrystalline Silicon Wafer | 650 |
| Square Diced Piece | 5mm×5mm | Single-Side Polished | Confirmed by Batch | Intrinsic Undoped Square Silicon Piece | 7 |
| Square Diced Piece | 10mm×10mm | Single-Side Polished | Confirmed by Batch | Intrinsic Undoped Square Silicon Piece | 10 |
| Square Diced Piece | 15mm×15mm | Single-Side Polished | Confirmed by Batch | Intrinsic Undoped Square Silicon Piece | 15 |
| Square Diced Piece | 20mm×20mm | Single-Side Polished | Confirmed by Batch | Intrinsic Undoped Square Silicon Piece | 18 |
| Round Diced Piece | Φ10mm | Single-Side Polished | Confirmed by Batch | Intrinsic Undoped Round Silicon Piece | 30 |
Reduces substrate parasitic conduction, signal coupling, and high-frequency transmission loss.
Used as substrates for terahertz transmission, antennas, waveguides, filters, and detectors.
Suitable for infrared optics, photodetection, silicon photonics, and optoelectronic integration.
Used for pressure, gas, biosensing, temperature, and inertial sensor fabrication.
Suitable for depositing metals, oxides, nitrides, two-dimensional materials, and polymer films.
Used for capacitors, dielectric layers, Hall-effect measurements, interfacial transport, and low-background electrical testing.
Check the size, polishing method, crystal orientation, resistivity, thickness, quantity, and packaging condition.
Wear powder-free gloves and handle the wafer by the edge using a vacuum wand or wafer tweezers.
Perform cleaning, dehydration, plasma treatment, or surface activation according to the downstream process.
After confirming equipment compatibility, proceed with coating, exposure, etching, deposition, or electrode fabrication.
Use an antistatic workbench, grounded equipment, and ESD-safe packaging to reduce charge accumulation.
Protect the polished surface before dicing and promptly remove silicon debris, fragments, and surface particles afterward.
Record the batch, resistivity, orientation, thickness, and all subsequent processing conditions.
Return unused products to a wafer box, self-sealing carrier, or clean bag and store them sealed.
Do not touch the central area with ordinary metal tools or place the polished surface directly on a rough worktop.
High-resistivity substrates dissipate charge less readily, so ESD protection is required during device processing and testing.
Open, handle, and process the wafers in a clean environment whenever possible to avoid dust, fingerprints, and organic contamination.
Thermal oxidation, diffusion, and annealing may affect the surface condition and some electrical parameters.
Both sides of a DSP wafer are functional surfaces and should be protected using dedicated wafer carriers and interleaf packaging.
Keep away from acidic or alkaline vapors, corrosive gases, and high humidity. Reseal promptly after opening.
It is a semiconductor substrate made from high-purity monocrystalline silicon. By minimizing intentional doping and the influence of background impurities, the wafer provides high resistivity, low free-carrier concentration, and a low electrical background.
Not exactly. “Intrinsic” describes material close to an intentionally undoped state, while “high resistivity” describes the electrical resistivity. Some high-resistivity wafers may still exhibit weak N-type or P-type conductivity; refer to the batch inspection data.
No. Undoped generally means that conventional dopants were not intentionally added. The crystal may still contain small amounts of oxygen, carbon, background impurities, and crystal defects.
Higher resistivity helps reduce substrate parasitic conduction, eddy-current loss, and electrical coupling between adjacent devices, improving isolation and transmission performance in some RF, microwave, and high-frequency structures.
Yes, but wafer resistivity, thickness, double-side polishing, surface parallelism, and transmission and loss requirements across the target frequency range must all be confirmed. DSP products are generally preferred for transmission experiments.
Yes, for certain infrared bands. Actual transmission and absorption also depend on the operating wavelength, wafer thickness, surface condition, free-carrier concentration, and surface reflection.
Choose SSP when coating, lithography, or device processing is performed on one side only. DSP is recommended for transmission measurements, wafer bonding, double-sided lithography, backside etching, and precision MEMS processing.
A 100 μm ultra-thin silicon wafer can bend, warp, or break easily. Reduce mechanical stress during handling, cleaning, drying, spin coating, and clamping, and use carriers, chucks, and packaging designed for ultra-thin wafers.
No. High resistivity can reduce substrate leakage and high-frequency loss, but excessively high resistivity may be unsuitable for devices requiring substrate conduction, backside electrodes, rapid electrostatic discharge, or a vertical current path.
Compared with low-resistivity wafers, high-resistivity silicon dissipates charge less readily through the substrate. ESD precautions are particularly important in dry or insulating environments; use grounded equipment and antistatic tools.
Yes. Clean, dehydrate, and prepare the surface according to the process requirements, and confirm that the wafer size, thickness, and flatness are compatible with the spin coater, aligner, and etching equipment.
Yes. Magnetron sputtering, evaporation, CVD, ALD, spin coating, and other deposition methods may be used for metals, oxides, nitrides, two-dimensional materials, and polymer films.
Yes. Thermal SiO₂, Si₃N₄, and other dielectric films can be customized. Film thickness, single-side or double-side processing, and thickness inspection requirements can also be specified.
Yes. Au, Pt, Ag, Cu, Al, Ti, Cr, and other metal films can be customized. Some metals have limited adhesion to silicon or oxide surfaces and may require a Ti or Cr adhesion layer.
Yes. Thermal oxidation consumes part of the surface silicon and may affect the surface condition and electrical behavior. For parameter-sensitive devices, include oxidation temperature and time in the overall thermal budget.
Yes. They can be processed into square, rectangular, round, or custom-shaped pieces using laser cutting, DISCO dicing, mechanical scribing, or drilling. Specify dimensions, thickness, tolerance, and quantity.
Mechanical or laser dicing may produce some edge chipping, particles, or localized thermal effects. For strict edge-quality requirements, specify the permitted chipping range and cleaning requirements in advance.
High-resistivity silicon is still a semiconductor, not an ideal insulator. For stronger electrical isolation, consider thermally oxidized silicon, SOI wafers, glass, quartz, or another insulating substrate.
Yes, as test samples or thin-film substrates, but the signal from the high-resistivity material itself may be weak. Good electrode contact, suitable sample dimensions, test current, and sufficient instrument sensitivity are important.
Resistivity is affected by crystal growth, background impurity distribution, measurement position, measurement temperature, and test method. Refer to the parameters and tolerances specified for the corresponding batch.
Crystal orientation, resistivity, thickness, polishing method, wafer dimensions, dicing specification, oxide layers, metal films, packaging, and inspection documentation can be customized according to the application.
A resistivity data sheet or inspection report may be available depending on the batch and order requirements. For strict resistivity ranges, specify the test method, measurement positions, and acceptance criteria before ordering.
Crystal orientation, thickness, TTV, bow, warp, surface quality, and related batch data may be available. Special inspection items must be specified before purchase.
Intrinsic high-resistivity silicon wafers generally consist of bulk high-resistivity monocrystalline silicon. SOI wafers consist of a top silicon layer, a buried oxide layer, and a handle silicon substrate; the buried oxide provides stronger electrical isolation.
Size + SSP/DSP + crystal orientation + target resistivity + thickness + quantity + dicing requirement + inspection requirement + packaging requirement.
Intrinsic high-resistivity monocrystalline silicon wafers provide high resistivity, low free-carrier concentration, low substrate leakage, and reduced high-frequency loss. They are suitable for RF and microwave devices, terahertz research, infrared optics, optoelectronics, MEMS, low-leakage devices, and fundamental semiconductor studies. SSP products are suitable for standard single-side processing, while DSP products are recommended for transmission measurements, double-sided lithography, and wafer bonding. For parameter-sensitive applications, specify resistivity, orientation, thickness, polishing method, and inspection requirements before purchase.
Covers intrinsic single-side and double-side polished silicon wafers, allowing direct price selection by size, thickness, N-type or P-type conductivity, and crystal orientation.
| Polishing System | Size | Specification | N-Type Silicon | P-Type Silicon | ||||
|---|---|---|---|---|---|---|---|---|
| Orientation 100 | Orientation 110 | Orientation 111 | Orientation 100 | Orientation 110 | Orientation 111 | |||
| Intrinsic SSP Single-Side Polished Silicon Wafer Square pieces, small round pieces, and 1–8 inch wafers | 5 × 5 mm | Single-Side Polished | $5 | $5 | $5 | $5 | $5 | $5 |
| Φ10 mm | Round SSP | $14 | $14 | $14 | $14 | $14 | $14 | |
| 10 × 10 mm | Single-Side Polished | $6 | $6 | $6 | $6 | $6 | $6 | |
| 15 × 15 mm | Single-Side Polished | $8 | $8 | $8 | $8 | $8 | $8 | |
| 20 × 20 mm | Single-Side Polished | $10 | $10 | $10 | $10 | $10 | $10 | |
| 1 Inch | Single-Side Polished | $40 | $40 | $40 | $40 | $40 | $40 | |
| 2 Inch | Standard-Thickness SSP | $40 | $40 | $40 | $40 | $40 | $40 | |
| 2 Inch | 100 μm Thick | $108 | $108 | $108 | $108 | $108 | $108 | |
| 3 Inch | Single-Side Polished | $57 | $57 | $57 | $57 | $57 | $57 | |
| 4 Inch | Single-Side Polished | $69 | $69 | $69 | $69 | $69 | $69 | |
| 5 Inch | Single-Side Polished | $99 | $99 | $99 | $99 | $99 | $99 | |
| 6 Inch | Single-Side Polished | $107 | $107 | $107 | $107 | $107 | $107 | |
| 8 Inch | Single-Side Polished | $221 | $221 | $221 | $221 | $221 | $221 | |
| Intrinsic DSP Double-Side Polished Silicon Wafer Double-side mirror polished; available in 2, 3, 4, and 6 inch wafers | 2 Inch | Double-Side Polished | $42 | $42 | $42 | $42 | $42 | $42 |
| 3 Inch | Double-Side Polished | $61 | $61 | $61 | $61 | $61 | $61 | |
| 4 Inch | Double-Side Polished | $73 | $73 | $73 | $73 | $73 | $73 | |
| 6 Inch | Double-Side Polished | $111 | $111 | $111 | $111 | $111 | $111 | |
Partial references citing our materials (from Google Scholar)
Carbon Dioxide Reduction
1. ACS Nano Strain Relaxation in Metal Alloy Catalysts Steers the Product Selectivity of Electrocatalytic CO2 Reduction
The bipolar membrane (Fumasep FBM) in this paper was purchased from SCI Materials Hub, which was used in rechargeable Zn-CO2 battery tests. The authors reported a strain relaxation strategy to determine lattice strains in bimetal MNi alloys (M = Pd, Ag, and Au) and realized an outstanding CO2-to-CO Faradaic efficiency of 96.6% with outstanding activity and durability toward a Zn-CO2 battery.
2. Front. Chem. Boosting Electrochemical Carbon Dioxide Reduction on Atomically Dispersed Nickel Catalyst
In this paper, Vulcan XC-72R was purchased from SCI Materials Hub. Vulcan XC 72R carbon is the most common catalyst support used in the anode and cathode electrodes of Polymer Electrolyte Membrane Fuel Cells (PEMFC), Direct Methanol Fuel Cells (DMFC), Alkaline Fuel Cells (AFC), Microbial Fuel Cells (MFC), Phosphoric Acid Fuel Cells (PAFC), and many more!
3. Adv. Mater. Partially Nitrided Ni Nanoclusters Achieve Energy-Efficient Electrocatalytic CO2 Reduction to CO at Ultralow Overpotential
An AEM membrane (Sustainion X37-50 Grade RT, purchased from SCI Materials Hub) was activated in 1 M KOH for 24 h, washed with ultra-purity water prior to use.
4. Adv. Funct. Mater. Nanoconfined Molecular Catalysts in Integrated Gas Diffusion Electrodes for High-Current-Density CO2 Electroreduction
In this paper (Supporting Information), an anion exchanged membrane (Fumasep FAB-PK-130 obtained from SCI Materials Hub (www.scimaterials.cn)) was used to separate the catholyte and anolyte chambers.
SCI Materials Hub: we also recommend our Fumasep FAB-PK-75 for the use in a flow cell.
5. Appl. Catal. B Efficient utilization of nickel single atoms for CO2 electroreduction by constructing 3D interconnected nitrogen-doped carbon tube network
In this paper, the Nafion 117 membrane was obtained from SCI Materials Hub.
In this paper, Proton exchange membrane (Nafion 117), Nafion D520, and Toray 060 carbon paper were purchased from SCI Materials Hub.
7. National Science Review Confinement of ionomer for electrocatalytic CO2 reduction reaction via efficient mass transfer pathways
An anion exchange membrane (PiperION-A15-HCO3) was obtained from SCI Materials Hub.
8. Catalysis Communications Facilitating CO2 electroreduction to C2H4 through facile regulating {100} & {111} grain boundary of Cu2O
Carbon paper (TGPH060), membrane solution (Nafion D520), and ionic membrane (Nafion N117) were obtained from Wuhu Eryi Material Technology Co., Ltd (a company under SCI Materials Hub).
Batteries
1. J. Mater. Chem. A Blocking polysulfides with a Janus Fe3C/N-CNF@RGO electrode via physiochemical confinement and catalytic conversion for high-performance lithium–sulfur batteries
Graphene oxide (GO) in this paper was obtained from SCI Materials Hub. The authors introduced a Janus Fe3C/N-CNF@RGO electrode consisting of 1D Fe3C decorated N-doped carbon nanofibers (Fe3C/N-CNFs) side and 2D reduced graphene oxide (RGO) side as the free-standing carrier of Li2S6 catholyte to improve the overall electrochemical performance of Li-S batteries.
This paper used more than 10 kinds of materials from SCI Materials Hub and the authors gave detailed properity comparsion.
The commercial IEMs of Fumasep FAB-PK-130 and Nafion N117 were obtained from SCI Materials Hub.
Gas diffusion layers of GDL340 (CeTech) and SGL39BC (Sigracet) and Nafion dispersion (Nafion D520) were obtained from SCI Materials Hub.
Zn foil (100 mm thickness) and Zn powder were obtained from the SCI Materials Hub.
Commercial 20% Pt/C, 40% Pt/C and IrO2 catalysts were also obtained from SCI Materials Hub.
3. Journal of Energy Chemistry Vanadium oxide nanospheres encapsulated in N-doped carbon nanofibers with morphology and defect dual-engineering toward advanced aqueous zinc-ion batteries
In this paper, carbon cloth (W0S1011) was obtained from SCI Materials Hub. The flexible carbon cloth matrix guaranteed the stabilization of the electrode and improved the conductivity of the cathode.
4. Energy Storage Materials Defect-abundant commercializable 3D carbon papers for fabricating composite Li anode with high loading and long life
The 3D carbon paper (TGPH060 raw paper) were purchased from SCI Materials Hub.
5. Nanomaterials A Stable Rechargeable Aqueous Zn–Air Battery Enabled by Heterogeneous MoS2 Cathode Catalysts
Nafion D520 (5 wt%), and carbon paper (GDL340) were received from SCI-Materials-Hub.
Carbon cloth (W0S1011) and other electrochemical consumables required for air cathode were provided by SCI Materials Hub.
Oxygen Reduction Reaction
1. J. Chem. Eng. Superior Efficiency Hydrogen Peroxide Production in Acidic Media through Epoxy Group Adjacent to Co-O/C Active Centers on Carbon Black
In this paper, Vulcan XC 72 carbon black, ion membrane (Nafion N115, 127 μL), Nafion solution (D520, 5 wt%), and carbon paper (AvCarb GDS 2230 and Spectracarb 2050A-1050) were purchased from SCI Materials Hub.
2. Journal of Colloid and Interface Science Gaining insight into the impact of electronic property and interface electrostatic field on ORR kinetics in alloy engineering via theoretical prognostication and experimental validation
The 20 wt% Pt3M (M = Cr, Co, Cu, Pd, Sn, and Ir) were purchased from SCI Materials Hub. This work places emphasis on the kinetics of the ORR concerning Pt3M (M = Cr, Co, Cu, Pd, Sn, and Ir) catalysts, and integrates theoretical prognostication and experimental validation to illuminate the fundamental principles of alloy engineering.
Water Electrolysis
1. International Journal of Hydrogen Energy Gold as an efficient hydrogen isotope separation catalyst in proton exchange membrane water electrolysis
The cathodic catalysts of Pt/C (20 wt%, 2–3 nm) and Au/C (20 wt%, 4–5 nm) were purchased from SCI Materials Hub.
2. Small Science Silver Compositing Boosts Water Electrolysis Activity and Durability of RuO2 in a Proton-Exchange-Membrane Water Electrolyzer
Two fiber felts (0.35 mm thickness, SCI Materials Hub) were used as the porous transport layers at both the cathode and the anode.
3. Advanced Functional Materials Hierarchical Crystalline/Amorphous Heterostructure MoNi/NiMoOx for Electrochemical Hydrogen Evolution with Industry-Level Activity and Stability
Anion-exchange membrane (FAA-3-PK-130) was obtained from SCI Materials Hub website.
Fuel Cells
1. Polymer Sub-two-micron ultrathin proton exchange membrane with reinforced mechanical strength
Gas diffusion electrode (60% Pt/C, Carbon paper) was purchased from SCI Materials Hub.
Characterization
1. Chemical Engineering Journal Electrochemical reconstitution of Prussian blue analogue for coupling furfural electro-oxidation with photo-assisted hydrogen evolution reaction
An Au nanoparticle film was deposited on the total reflecting plane of a single reflection ATR crystal (SCI Materials Hub, Wuhu, China) via sputter coater.
|
We Provide A Broad Range of Materials, Instruments & Solutions in Advanced Science and Technologies | About Us |
