SciMater™ SOI Insulated Silicon Wafer-SCI Materials Hub

Product Overview

SOI stands for Silicon on Insulator. Its structure consists of a device silicon layer, a buried oxide (BOX) layer, and a silicon handle wafer. The top silicon acts as the device layer, the BOX layer provides electrical isolation, and the handle wafer provides mechanical support and enables backside processing.

SOI products can be configured with different device-layer conductivity types, crystal orientations, resistivity ranges, thicknesses, BOX thicknesses, and handle-wafer parameters for silicon photonics, integrated circuits, MEMS, RF devices, sensors, and thin-film research.

Before ordering, confirm the device-layer type, orientation, dopant, resistivity, and thickness; BOX thickness; handle-wafer type, orientation, dopant, resistivity, and thickness; and polishing configuration.

Key Features

Strong Electrical Isolation The BOX layer isolates the device layer from the handle wafer, helping reduce substrate leakage and parasitic coupling.

Configurable Device Layer The top silicon can be specified by conductivity type, crystal orientation, resistivity, and thickness.

Low Parasitic Capacitance Suitable for low-power, high-speed, RF, and high-sensitivity device research.

Precision Processing Compatible Compatible with photolithography, etching, thinning, oxidation, coating, bonding, and dicing.

SOI Three-Layer Structure

Device Silicon Layer The primary device layer. Its conductivity type, orientation, resistivity, and thickness can be controlled for transistors, waveguides, sensors, and micromechanical structures.

Buried Oxide (BOX) Layer Located between the device layer and handle wafer, the BOX provides electrical isolation and may also function as an etch-stop, sacrificial, thermal-isolation, or optical-confinement layer.

Silicon Handle Wafer Provides mechanical support for the wafer and may also be used for backside etching, electrical contact, bonding, and device packaging.

Complete Product Specifications and Price Comparison

This table compares 4-inch, 6-inch, and 8-inch full SOI wafers with custom-cut pieces identified as Parameters 1, 2, 4, 5, 6, and 8. Cut-piece data follows the corresponding product parameter records.

Product Category	Size	Parameter ID	Polishing	Device-Layer Type	Device-Layer Orientation	Device-Layer Dopant	Device-Layer Resistivity (Ω·cm)	Device-Layer Thickness	BOX Thickness	Handle-Wafer Type	Handle-Wafer Orientation	Handle-Wafer Dopant	Handle-Wafer Resistivity (Ω·cm)	Handle-Wafer Thickness	Price (CNY)
Full SOI Wafer	4 Inch	—	Single-Side Polished	N-Type	<100>	—	0.01–0.05	4.5μm	0.5μm	N-Type	<100>	—	1–25.5	525μm	¥4810
		—	Single-Side Polished	N-Type	<100>	—	0.3–1.2	1.5μm	1μm	N-Type	<100>	—	0.3–1.2	725μm	¥4810
		—	Single-Side Polished	N-Type	<100>	—	1–5	2.5μm	1μm	P-Type	<100>	—	1–20	725μm	¥4810
		—	Single-Side Polished	P-Type	<100>	—	1–10	1.5μm	1μm	P-Type	<100>	—	1–10	525μm	¥4810
		—	Single-Side Polished	P-Type	<100>	—	3–8	2.2μm	1.1μm	P-Type	<100>	—	3–8	525μm	¥4810
		—	Single-Side Polished	P-Type	<100>	—	3–8	2.2μm	1.1μm	P-Type	<100>	—	4–7	525μm	¥4810
		—	Double-Side Polished	N-Type	<100>	—	0.01–0.02	5μm	1μm	N-Type	<100>	—	1–10	400μm	¥6410
Full SOI Wafer	6 Inch	—	Single-Side Polished	P-Type	<100>	—	1–20	0.2μm	0.12μm	P-Type	<100>	—	1–20	675μm	¥6010
		—	Single-Side Polished	P-Type	<100>	—	1–20	0.2μm	0.375μm	P-Type	<100>	—	1–20	675μm	¥6010
		—	Single-Side Polished	P-Type	<100>	—	1–20	2μm	0.5μm	P-Type	<100>	—	1–20	675μm	¥6010
		—	Single-Side Polished	P-Type	<100>	—	＜0.02	60μm	2μm	P-Type	<100>	—	＜0.005	450μm	¥6010
		—	Double-Side Polished	P-Type	<100>	—	1–20	52μm	2μm	P-Type	<100>	—	1–20	575μm	¥6010
Full SOI Wafer	8 Inch	—	Single-Side Polished	N-Type	<100>	—	0.3–1.2	1.5μm	1μm	N-Type	<100>	—	0.3–1.2	725μm	¥9010
Full SOI Wafer	8 Inch	—	Single-Side Polished	P-Type	<100>	—	1–20	220nm	3μm	Not Specified	<100>	—	1–20	725μm	¥13610
SOI Cut Piece	10×10mm	Parameter 1	Single-Side Polished	N-Type	<100>	P	0.01–0.02	4.5μm	500nm	N-Type	<100>	P	1–30	525μm	¥210
		Parameter 2	Single-Side Polished	N-Type	<100>	P	1–5	2.5μm	500nm	P-Type	<100>	B	1–20	725μm	¥210
		Parameter 4	Single-Side Polished	P-Type	<100>	B	8–12	220nm	3μm	P-Type	<100>	B	750	725μm	¥210
		Parameter 5	Double-Side Polished	N-Type	<100>	P	＜0.02	40μm	1μm	N-Type	<100>	P	＜0.02	400μm	¥210
		Parameter 6	Single-Side Polished	N-Type	<100>	P	0.3–1.2	1.5μm	1μm	N-Type	<100>	P	0.3–1.2	725μm	¥210
SOI Cut Piece	20×20mm	Parameter 8	Single-Side Polished	P-Type	<100>	B	8–12	220nm	3μm	P-Type	<100>	B	750	725μm	¥810

Parameters 1, 2, 4, 5, 6, and 8 for the cut pieces follow the corresponding parameter records; the original P and B dopant designations are retained. Tolerances, surface quality, TTV, Bow, Warp, inspection documentation, and packaging requirements for full wafers and cut pieces are subject to final order confirmation.

Applications

MEMS For microcantilevers, membranes, microheaters, inertial devices, pressure sensors, and micromechanical structures.

Silicon Photonics and Optoelectronics For silicon waveguides, modulators, couplers, photodetectors, and photonic integrated devices.

RF and Microwave Devices Helps reduce substrate coupling, parasitic capacitance, and leakage in high-frequency and low-power structures.

Integrated Circuits For low-power CMOS, fully depleted devices, isolation structures, and specialized integrated-circuit research.

Sensors Suitable for pressure, gas, biological, temperature, acceleration, and optical sensors.

Microfluidics and Lab-on-a-Chip The BOX can function as an etch-stop or insulating layer for microchannels, microreactors, and chip packaging.

Power and High-Voltage Devices Thick device layers or low-resistivity structures can support power devices, isolated devices, and specialized electrode structures.

Materials and Thin-Film Research For deposition of metals, oxides, nitrides, two-dimensional materials, and functional thin films.

Research and Process Validation For SOI structure studies, etching-process development, device design, and micro-/nanofabrication training.

Selection Guide

Application Requirement	Recommended Selection
Thin-Layer Devices and Silicon Photonics	Select SOI with a 220 nm or 0.2 μm device layer and choose the BOX thickness according to the optical mode and device structure.
General Micro-/Nanodevices	Select SOI with a 1.5–5 μm device layer for photolithography, shallow etching, sensors, and integrated structures.
MEMS Mechanical Structures	Select SOI with a 40–60 μm device layer for microbeams, membranes, proof masses, and deep silicon etching.
Low-Resistance Conductive Structures	Choose a lower-resistivity device layer or handle wafer and confirm the metal-electrode and backside-contact design.
Double-Side Processing and Bonding	Choose double-side polished SOI and confirm handle-wafer thickness, TTV, Bow, Warp, and backside quality.
Small-Area Experiments	Choose a 10 × 10 mm or 20 × 20 mm cut piece and verify the complete three-layer structure by parameter ID.
Precision Device Fabrication	Confirm device-layer thickness uniformity, BOX thickness, particle requirements, crystal orientation, and wafer flatness.

How to Use

1 Verify Layer Parameters Verify the device layer, BOX, handle wafer, polishing, orientation, resistivity, thickness, and quantity.

2 Identify the Device Side Use the package label and parameter documentation; do not identify the device side solely by color or reflectivity.

3 Clean Handling Wear powder-free gloves and handle the wafer by its edge using a vacuum wand or dedicated tweezers.

4 Pre-Process Cleaning Select a cleaning process compatible with silicon and SiO₂ according to lithography, bonding, or deposition requirements.

5 Lithography and Etching Set the etch depth according to the device-layer thickness and use the BOX as an insulating or etch-stop layer.

6 Structure Release When locally removing the BOX, control lateral undercut, structural stress, and release time.

7 Dicing and Cutting Protect the device side before cutting and remove silicon debris, particles, and residues promptly afterward.

8 Record Process Conditions Record the batch, layer thicknesses, cleaning conditions, etch depth, and thermal-processing history.

Handling, Cleaning, and Storage

Cleaning & Storage	Recommended Practice
Prevent Device-Layer Scratches	The top silicon is the primary device layer and should not contact rough surfaces, ordinary paper, or sharp tools.
Control Etch Depth	For thin device layers, define the etch endpoint accurately to avoid etching through the device layer or damaging the BOX.
Control Fluorine-Based Processes	Fluorine-based etchants attack SiO₂; evaluate BOX exposure time and lateral undercut.
Control the Thermal Budget	High-temperature oxidation, diffusion, and annealing may alter device-layer thickness, dopant distribution, and interface condition.
Protect Both Polished Surfaces	Both surfaces of double-side polished wafers require protection from vacuum-chuck marks, particles, and scratches.
Clean and Dry Storage	Return unused wafers to a wafer box or clean carrier and protect them from high humidity, acidic or alkaline vapors, and particle contamination.

FAQ

1. What is an SOI wafer?

An SOI wafer consists of a monocrystalline device silicon layer, a buried oxide (BOX) layer, and a silicon handle wafer. The top silicon is used to fabricate devices, the BOX provides electrical isolation, and the handle wafer provides mechanical support.

2. How does an SOI wafer differ from a conventional monocrystalline silicon wafer?

A conventional silicon wafer is generally a continuous monocrystalline silicon substrate. SOI includes an internal BOX layer that can reduce leakage, parasitic capacitance, and substrate coupling between devices.

3. How should the device-layer thickness be selected?

A 220 nm to 0.2 μm device layer is suitable for silicon photonics and thin-layer devices; 1.5–5 μm is suitable for general micro-/nanodevices; and 40–60 μm is suitable for MEMS mechanical structures and deep silicon etching.

4. What is the function of the BOX layer?

The BOX primarily provides electrical isolation and may also serve as an etch-stop, sacrificial, optical-confinement, or thermal-isolation layer.

5. How should single-side and double-side polishing be selected?

Single-side polished SOI is suitable when processing only the device side. Double-side polished SOI is recommended for backside exposure, backside etching, double-side bonding, or precision MEMS fabrication.

6. Can SOI wafers be used directly for photolithography and etching?

Yes. Clean and dehydrate the wafer according to the process requirements, then set the etch depth and endpoint based on the device-layer thickness, target structure, and BOX position.

7. Can the BOX layer be removed?

Yes. The BOX can be removed locally or entirely using an SiO₂-compatible etching system, but lateral undercut and structural release time must be controlled in fluorine-based processes.

8. How should the parameters of SOI cut pieces be confirmed?

Confirm the complete structure by parameter ID, including device-layer type, orientation, dopant, resistivity, thickness, BOX thickness, handle-wafer parameters, and polishing.

9. Can additional coatings or oxidation be applied to an SOI wafer?

Yes. Thermal oxidation, dielectric-film deposition, and metal coating are possible, but high-temperature processing may affect device-layer thickness, dopant distribution, and interface condition.

10. Are inspection documents and custom parameters available?

Device-layer thickness, BOX thickness, resistivity, handle-wafer thickness, TTV, Bow, Warp, and surface-quality documentation can be confirmed according to the batch and order.

Ordering Information

Recommended inquiry format:

Size + Single-/Double-Side Polished + Device-Layer Type + Orientation + Dopant + Device-Layer Resistivity + Device-Layer Thickness + BOX Thickness + Handle-Wafer Type + Orientation + Dopant + Handle-Wafer Resistivity + Handle-Wafer Thickness + Quantity + Processing Requirements

Example: 6 inch + single-side polished + P-type<100>device layer + 1–20 Ω·cm + 2 μm device-layer thickness + 0.5 μm BOX + P-type<100>handle wafer + 1–20 Ω·cm + 675 μm handle-wafer thickness + 10 wafers.

Product Summary

SciMater™ SOI wafers use a three-layer device-silicon/BOX/handle-silicon structure to provide effective electrical isolation between the device layer and substrate. They offer low leakage, low parasitic capacitance, low-power compatibility, and strong micro-/nanofabrication compatibility. Thin device layers are suitable for silicon photonics, integrated circuits, and thin-layer devices; thick device layers are suitable for MEMS and deep silicon etching; and double-side polished options are suitable for backside processing, bonding, and precision structure fabrication. Confirm all three-layer parameters before purchasing.