High-purity monocrystalline silicon substrates for integrated circuits, microelectronic devices, MEMS, sensors, optoelectronics, thin-film deposition, micro- and nanofabrication, and university research.
SciMater™ Single-Side and Double-Side Polished Monocrystalline Silicon Wafers are manufactured from high-purity single-crystal silicon through slicing, edge rounding, lapping, cleaning, and chemical-mechanical polishing. They are suitable for semiconductor devices, thin-film materials, photolithography, etching, MEMS, sensors, and micro-/nanostructure fabrication.
A single-side polished wafer, abbreviated SSP, has one precision-polished surface. Its back surface is generally lapped, etched, or otherwise process-finished. SSP wafers are suitable for most single-sided lithography, coating, etching, and material-growth experiments.
A double-side polished wafer, abbreviated DSP, has both front and back surfaces precision polished. DSP wafers are recommended for double-sided processing, transmission measurements, wafer bonding, deep silicon etching, microfluidics, and applications requiring improved overall flatness.
Standard wafer sizes from 1 to 8 inches are available. N-type, P-type, intrinsic undoped,<100>,<111>, multiple resistivity ranges, thicknesses, and orientation features can be confirmed according to project requirements. Final specifications are subject to the batch label, inspection documentation, or confirmed order.
| Comparison Item | Single-Side Polished Wafer | Double-Side Polished Wafer |
|---|---|---|
| Abbreviation | SSP, Single-Side Polished | DSP, Double-Side Polished |
| Polished Surfaces | One precision-polished surface | Both front and back surfaces precision polished |
| Back-Surface Condition | Lapped, etched, or process-finished | Precision-polished surface |
| Relative Cost | Lower | Higher |
| Main Advantage | Cost-effective for most routine microfabrication and thin-film experiments | Both surfaces are flat and smooth for double-sided processing, bonding, and transmission measurements |
| Typical Applications | Lithography, coating, etching, material growth, and routine device fabrication | Wafer bonding, double-sided lithography, deep silicon etching, MEMS, and optical testing |
| Equipment Use | Compatible with most standard wafer equipment and vacuum chucks | The back polished surface must be protected from chuck marks and particle scratches |
| Recommended For | General research, material deposition, and single-sided device processing | Double-sided processing, transmission, bonding, or high-flatness applications |
| Wafer Size | Nominal Diameter | SSP Reference Price (CNY / Wafer) | DSP Reference Price (CNY / Wafer) |
|---|---|---|---|
| 1 Inch | Ø25.4 mm | CNY 30 | CNY 40 |
| 2 Inch | Ø50.8 mm | CNY 40 | CNY 50 |
| 3 Inch | Ø76.2 mm | CNY 60 | CNY 70 |
| 4 Inch | Ø100 mm | CNY 80 | CNY 90 |
| 5 Inch | Ø125 mm | CNY 85 | CNY 90 |
| 6 Inch | Ø150 mm | CNY 90 | CNY 95 |
| 8 Inch | Ø200 mm | CNY 105 | CNY 150 |
| Parameter | Standard Options |
|---|---|
| Material | High-purity monocrystalline silicon |
| Polishing | Single-side polished or double-side polished |
| Wafer Size | 1, 2, 3, 4, 5, 6, and 8 inches |
| Conductivity Type | N-type, P-type, or intrinsic undoped |
| Common Dopants | Phosphorus for N-type and boron for P-type |
| Crystal Orientation | <100>and<111>; other orientations may be available |
| Resistivity | Low, standard, high, or customized resistivity ranges |
| Thickness | Standard, ultra-thin, extra-thick, or customized thickness |
| Surface Condition | Bare polished silicon; optional SiO₂, Si₃N₄, or metal coatings |
| Orientation Feature | Primary flat, primary/secondary flats, notch, or size-dependent standard |
| Flatness Parameters | Thickness tolerance, TTV, Bow, and Warp may be specified |
| Cutting Services | Square, rectangular, circular, mechanical dicing, laser cutting, drilling, and special shapes |
| Packaging | Single-wafer box, multi-wafer box, vacuum packaging, clean bag, or customized packaging |
| Parameter | Meaning and Selection Guidance |
|---|---|
| Conductivity Type | Electrons are the primary carriers in N-type silicon, while holes are the primary carriers in P-type silicon. Select according to the device architecture and test plan. |
| Crystal Orientation | <100>is widely used in integrated circuits, MOS, and MEMS;<111>is often used for epitaxy, surface studies, and selected orientation-dependent etching. |
| Resistivity | Low resistivity supports conductive substrates; high resistivity supports low-leakage, RF, microwave, and insulation-related experiments. |
| Thickness | Standard thickness is easy to handle; ultra-thin wafers support special devices; thick wafers improve mechanical support and deep processing. |
| TTV | Total Thickness Variation describes thickness uniformity across different wafer locations. |
| Bow | The center displacement of a free, unclamped wafer relative to a reference plane. |
| Warp | The overall difference between the wafer's highest and lowest points. |
| Surface Roughness | Smoother surfaces are better suited for fine lithography, ultrathin-film deposition, bonding, and micro-/nanodevice fabrication. |
| Application Requirement | Recommended Product |
|---|---|
| Front-side lithography, coating, or etching only | Single-side polished wafer |
| General material growth or thin-film characterization | Single-side polished wafer |
| Lower experimental cost | Single-side polished wafer |
| Processing required on both surfaces | Double-side polished wafer |
| Wafer bonding | Double-side polished wafer |
| Double-sided lithography or deep silicon etching | Double-side polished wafer |
| Transmission optical measurements | Double-side polished wafer |
| MEMS membrane structures or microchannels | Double-side polished wafer preferred |
| Application Scenario | Recommended Size |
|---|---|
| Small-area materials tests, teaching, and low-volume sample preparation | 1-inch, 2-inch, or cut pieces |
| Routine laboratory lithography, coating, and device fabrication | 2-inch or 3-inch |
| University micro-/nanofabrication platforms and semiconductor processing | 4-inch |
| Larger-area films, pilot processing, and device arrays | 5-inch or 6-inch |
| Large-area semiconductor processes and industrial equipment | 8-inch |
| Small-area testing only | 5 mm × 5 mm, 10 mm × 10 mm, or 20 mm × 20 mm cut pieces |
| Cleaning Item | Recommendation |
|---|---|
| Organic Contamination | Use a process-compatible organic solvent and prevent solvent residue. |
| Particle Contamination | Use deionized-water rinsing, ultrasonic, or megasonic cleaning; use ultrasonic cleaning cautiously with ultra-thin wafers. |
| Native Oxide | Bare silicon naturally develops an oxide layer in air. Sensitive interface experiments require planned surface treatment. |
| Metal Contamination | Use clean vessels and high-purity reagents to reduce adverse effects on semiconductor-device performance. |
| Ultra-Thin Wafers | Reduce mechanical stress during cleaning, drying, and handling to prevent breakage and warpage. |
| DSP Wafers | Both surfaces are functional surfaces; do not place them directly on rough benches or ordinary paper. |
| Storage Item | Recommendation |
|---|---|
| Environment | Clean, dry, and protected from light; keep away from acidic, alkaline, and corrosive vapors. |
| Packaging | Keep unused wafers in the original wafer box, clean bag, or vacuum packaging. |
| Surface Protection | Prevent polished surfaces from contacting hard objects, paper fibers, plastic debris, or other wafers. |
| Opened Packages | Use promptly after opening; reseal remaining wafers and record the batch and opening date. |
| Long-Term Storage | Use a clean, dry cabinet and control humidity and particle contamination. |
| DSP Wafers | Use spaced or non-contact packaging to prevent the two polished surfaces from rubbing. |
Please provide the following information when requesting a quotation:
Standard example: 4 inch + double-side polished + P-type +<100>+ 1–10 Ω·cm + 525 μm thickness + 25 wafers + individually packed.
For custom cutting: target dimensions + thickness + quantity + dimensional tolerance + cutting method + cleaning + packaging.
For custom coating: coating material + coating thickness + single-/double-side coating + adhesion-layer requirement + quantity.
An SSP wafer has one primary precision process surface and is less expensive, making it suitable for routine lithography, coating, and etching. A DSP wafer has two polished surfaces and is recommended for double-sided processing, bonding, transmission measurements, and high-precision MEMS.
Not necessarily. DSP only indicates that both surfaces are precision polished. It does not mean that every electrical or geometric parameter is automatically superior. Select DSP when the back surface must function as a process surface.
Choose according to the device architecture, carrier type, and electrical test plan. For general deposition or morphology studies, conductivity type may be less critical, so cost and available stock may be prioritized.
<100>is commonly used for MOS devices, integrated circuits, and MEMS.<111>is often used in selected epitaxy, surface science, orientation-dependent etching, and specialized device research.
Standard wafers are generally supplied as bare polished silicon, although a thin native oxide forms naturally in air. A specified thermal SiO₂ layer requires a separate oxidized-wafer product or custom oxidation process.
Availability depends on wafer size and batch. Intrinsic undoped wafers support low-carrier-background experiments, low-resistivity wafers support conductive substrates, and high-resistivity wafers support RF, microwave, low-leakage, and insulation-related research.
These options can be evaluated according to dimensions, thickness, tolerance, and quantity. Ultra-thin wafers are fragile, while extra-thick wafers require verification of fixture and vacuum-chuck compatibility.
Cleaning, dehydration, and surface preparation are recommended before use. High-precision lithography that is sensitive to particles, organics, or metal contamination should not use unverified wafers directly.
SiO₂, Si₃N₄, Au, Pt, Ag, Cu, Al, and other coatings can be evaluated. Adhesion layers, film thickness, single-/double-side coating, and patterning requirements should be confirmed with the order.
Pricing also depends on grade, SSP or DSP processing, conductivity type, orientation, resistivity, thickness, TTV, Bow, Warp, surface quality, inspection requirements, cutting, and packaging quantity.
Covers 2-inch to 6-inch double-side ground silicon wafers. Prices can be selected by wafer size, conductivity type, and crystal orientation 100, 110, or 111.
| Product Series | Size | Surface Condition | N-Type Price | P-Type Price | ||||
|---|---|---|---|---|---|---|---|---|
| Orientation 100 | Orientation 110 | Orientation 111 | Orientation 100 | Orientation 110 | Orientation 111 | |||
Double-Side Ground Double-Side Ground · Unpolished Silicon Wafer Covers 2-inch to 6-inch wafers with N-type, P-type, and orientations 100, 110, and 111. | 2 Inch | Double-Side Ground | $12 | $12 | $12 | $12 | $12 | $12 |
| 3 Inch | Double-Side Ground | $14 | $14 | $14 | $14 | $14 | $14 | |
| 4 Inch | Double-Side Ground | $16 | $16 | $16 | $16 | $16 | $16 | |
| 5 Inch | Double-Side Ground | $18 | $18 | $18 | $18 | $18 | $18 | |
| 6 Inch | Double-Side Ground | $22 | $22 | $22 | $22 | $22 | $22 | |
Partial references citing our materials (from Google Scholar)
Carbon Dioxide Reduction
1. ACS Nano Strain Relaxation in Metal Alloy Catalysts Steers the Product Selectivity of Electrocatalytic CO2 Reduction
The bipolar membrane (Fumasep FBM) in this paper was purchased from SCI Materials Hub, which was used in rechargeable Zn-CO2 battery tests. The authors reported a strain relaxation strategy to determine lattice strains in bimetal MNi alloys (M = Pd, Ag, and Au) and realized an outstanding CO2-to-CO Faradaic efficiency of 96.6% with outstanding activity and durability toward a Zn-CO2 battery.
2. Front. Chem. Boosting Electrochemical Carbon Dioxide Reduction on Atomically Dispersed Nickel Catalyst
In this paper, Vulcan XC-72R was purchased from SCI Materials Hub. Vulcan XC 72R carbon is the most common catalyst support used in the anode and cathode electrodes of Polymer Electrolyte Membrane Fuel Cells (PEMFC), Direct Methanol Fuel Cells (DMFC), Alkaline Fuel Cells (AFC), Microbial Fuel Cells (MFC), Phosphoric Acid Fuel Cells (PAFC), and many more!
3. Adv. Mater. Partially Nitrided Ni Nanoclusters Achieve Energy-Efficient Electrocatalytic CO2 Reduction to CO at Ultralow Overpotential
An AEM membrane (Sustainion X37-50 Grade RT, purchased from SCI Materials Hub) was activated in 1 M KOH for 24 h, washed with ultra-purity water prior to use.
4. Adv. Funct. Mater. Nanoconfined Molecular Catalysts in Integrated Gas Diffusion Electrodes for High-Current-Density CO2 Electroreduction
In this paper (Supporting Information), an anion exchanged membrane (Fumasep FAB-PK-130 obtained from SCI Materials Hub (www.scimaterials.cn)) was used to separate the catholyte and anolyte chambers.
SCI Materials Hub: we also recommend our Fumasep FAB-PK-75 for the use in a flow cell.
5. Appl. Catal. B Efficient utilization of nickel single atoms for CO2 electroreduction by constructing 3D interconnected nitrogen-doped carbon tube network
In this paper, the Nafion 117 membrane was obtained from SCI Materials Hub.
In this paper, Proton exchange membrane (Nafion 117), Nafion D520, and Toray 060 carbon paper were purchased from SCI Materials Hub.
7. National Science Review Confinement of ionomer for electrocatalytic CO2 reduction reaction via efficient mass transfer pathways
An anion exchange membrane (PiperION-A15-HCO3) was obtained from SCI Materials Hub.
8. Catalysis Communications Facilitating CO2 electroreduction to C2H4 through facile regulating {100} & {111} grain boundary of Cu2O
Carbon paper (TGPH060), membrane solution (Nafion D520), and ionic membrane (Nafion N117) were obtained from Wuhu Eryi Material Technology Co., Ltd (a company under SCI Materials Hub).
Batteries
1. J. Mater. Chem. A Blocking polysulfides with a Janus Fe3C/N-CNF@RGO electrode via physiochemical confinement and catalytic conversion for high-performance lithium–sulfur batteries
Graphene oxide (GO) in this paper was obtained from SCI Materials Hub. The authors introduced a Janus Fe3C/N-CNF@RGO electrode consisting of 1D Fe3C decorated N-doped carbon nanofibers (Fe3C/N-CNFs) side and 2D reduced graphene oxide (RGO) side as the free-standing carrier of Li2S6 catholyte to improve the overall electrochemical performance of Li-S batteries.
This paper used more than 10 kinds of materials from SCI Materials Hub and the authors gave detailed properity comparsion.
The commercial IEMs of Fumasep FAB-PK-130 and Nafion N117 were obtained from SCI Materials Hub.
Gas diffusion layers of GDL340 (CeTech) and SGL39BC (Sigracet) and Nafion dispersion (Nafion D520) were obtained from SCI Materials Hub.
Zn foil (100 mm thickness) and Zn powder were obtained from the SCI Materials Hub.
Commercial 20% Pt/C, 40% Pt/C and IrO2 catalysts were also obtained from SCI Materials Hub.
3. Journal of Energy Chemistry Vanadium oxide nanospheres encapsulated in N-doped carbon nanofibers with morphology and defect dual-engineering toward advanced aqueous zinc-ion batteries
In this paper, carbon cloth (W0S1011) was obtained from SCI Materials Hub. The flexible carbon cloth matrix guaranteed the stabilization of the electrode and improved the conductivity of the cathode.
4. Energy Storage Materials Defect-abundant commercializable 3D carbon papers for fabricating composite Li anode with high loading and long life
The 3D carbon paper (TGPH060 raw paper) were purchased from SCI Materials Hub.
5. Nanomaterials A Stable Rechargeable Aqueous Zn–Air Battery Enabled by Heterogeneous MoS2 Cathode Catalysts
Nafion D520 (5 wt%), and carbon paper (GDL340) were received from SCI-Materials-Hub.
Carbon cloth (W0S1011) and other electrochemical consumables required for air cathode were provided by SCI Materials Hub.
Oxygen Reduction Reaction
1. J. Chem. Eng. Superior Efficiency Hydrogen Peroxide Production in Acidic Media through Epoxy Group Adjacent to Co-O/C Active Centers on Carbon Black
In this paper, Vulcan XC 72 carbon black, ion membrane (Nafion N115, 127 μL), Nafion solution (D520, 5 wt%), and carbon paper (AvCarb GDS 2230 and Spectracarb 2050A-1050) were purchased from SCI Materials Hub.
2. Journal of Colloid and Interface Science Gaining insight into the impact of electronic property and interface electrostatic field on ORR kinetics in alloy engineering via theoretical prognostication and experimental validation
The 20 wt% Pt3M (M = Cr, Co, Cu, Pd, Sn, and Ir) were purchased from SCI Materials Hub. This work places emphasis on the kinetics of the ORR concerning Pt3M (M = Cr, Co, Cu, Pd, Sn, and Ir) catalysts, and integrates theoretical prognostication and experimental validation to illuminate the fundamental principles of alloy engineering.
Water Electrolysis
1. International Journal of Hydrogen Energy Gold as an efficient hydrogen isotope separation catalyst in proton exchange membrane water electrolysis
The cathodic catalysts of Pt/C (20 wt%, 2–3 nm) and Au/C (20 wt%, 4–5 nm) were purchased from SCI Materials Hub.
2. Small Science Silver Compositing Boosts Water Electrolysis Activity and Durability of RuO2 in a Proton-Exchange-Membrane Water Electrolyzer
Two fiber felts (0.35 mm thickness, SCI Materials Hub) were used as the porous transport layers at both the cathode and the anode.
3. Advanced Functional Materials Hierarchical Crystalline/Amorphous Heterostructure MoNi/NiMoOx for Electrochemical Hydrogen Evolution with Industry-Level Activity and Stability
Anion-exchange membrane (FAA-3-PK-130) was obtained from SCI Materials Hub website.
Fuel Cells
1. Polymer Sub-two-micron ultrathin proton exchange membrane with reinforced mechanical strength
Gas diffusion electrode (60% Pt/C, Carbon paper) was purchased from SCI Materials Hub.
Characterization
1. Chemical Engineering Journal Electrochemical reconstitution of Prussian blue analogue for coupling furfural electro-oxidation with photo-assisted hydrogen evolution reaction
An Au nanoparticle film was deposited on the total reflecting plane of a single reflection ATR crystal (SCI Materials Hub, Wuhu, China) via sputter coater.
|
We Provide A Broad Range of Materials, Instruments & Solutions in Advanced Science and Technologies | About Us |
